Optimal Design of Megabyte Second-Level Caches for Minimizing Bus Traffic in Shared-Memory Shared-Bus Multiprocessors

As the design of shared-memory sharedbus multiprocessors is heading toward employing megabyte second-level caches, how to optimize the design of the second-level caches in order to minimize the traffic on the shared memory bus and thus improve system scalability is of great interest. This paper presents a comprehensive study on this issue through extensive trace-driven simulation. The simulation results show that a good cache design could mean a reduction of bus traffic by more than 80 percent or, equivalently, an increase of system scalability by more than five times. Furthermore, they show that a few simple design guidelines can be derived because the optimal choice of cache configuration metrics exhibits a high degree of invariance over system-conf,guration variations. This research was sponsored by the National Science Council of R.O.C. under grant NSC 79-0408-E-002-10. @ 1994 The USENIX Association, computing systems, vol. 7 . No. 3 . summer 1994 393